J-SAP1 - Simple As Possible CPU - HTML/CSS/Javascript/jQuery (v 2018.09.21a)
ComponentBusComponent
Clock (clk)
ActionsParametersIndicator (leading edge)Control
delay(ms)  clock signal HLT
Memory Address Register (mar)
Address Select (manual / bus)Manual AddressAddress ValueControl
MI
RAM Memory - 16 bytes (ram)
ProgramManual Value InputRam ValueControl
RI  RO
Instruction Register (ir)
Instruction (blue) / Operand (yellow)InstructionControl
--- II IO
Instruction Decoder (id)
ActionsInstruction Step Counter (trailing edge clock pulse)Time Step
T0 T1 T2 T3 T4 T5
Micro Code (mc)
ActionsAddress SelectManual Address (unused bit, 4-bit instruction code / 3-bit step)
0  /
ProgramManual Value Input
Control Word
H
L
T		 M
I		 R
I		 R
O		 I
O		 I
I		 A
I		 A
O		 Σ
O		 S
U		 B
I		 O
I		 C
E		 C
O		 J F
I
Address Bus Value
Program Counter (pc) (leading edge clock pulse)
ControlValue
CO  J  CE
Arithmetic Logic Unit (alu)
ControlValue
ΣO  SU
CPU Flags Register (flag)
ControlValues
FI CF  ZF
Register 'A' (ra)
ControlValue
AO  AI
Register 'B' (rb)
ControlValue
BI
Output (output)
ControlValue
OI  000